Digital clock manager

A digital clock manager is a function for manipulating clock signals by: ^[1]

• Multiply and divide an incoming clock (DFS).
• Recondition a clock to, for example, ensure 50% duty cycle.
• Phase shift (DLL).
• Eliminate clock skew.

See also

• Clock signal
• Delay-locked loop
• Phase-locked loop
• Field-programmable gate array (DCM is used in FPGA)

References

1. ^ "Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs". http://www.xilinx.com/support/documentation/application_notes/xapp462.pdf.  070804 xilinx.com